Synthetic Instruments (SI) allow multiple functions to be synthesized from a limited set of “generic” SI components, as opposed to discrete instrument types such as a spectrum analyzer. Examples of generic components include Down Converters (DCs), digitizers, Up Converters (UCs), and Arbitrary Waveform Generators (AWGs).
The stimulus functionality of a SI comprises a digital source, Digital to Analog Converter (DAC), and an Up Converter (UC). The DAC can reside on an AWG providing the baseband/Intermediate Frequency (IF) source to the UC. The digital source provides the flexible modulation functionality while the UC provides the frequency translation functionality.
Digital Signal Processing (DSP) plays a central role in the implementation of SIs. Moving as many signal processing tasks as possible from the analog domain to the digital domain makes for a more flexible system, such as by adding programmability. Advances in DSP can also be exploited to reduce the complexity of, or remove, the analog components. As known in the art, DSP-oriented functions can be implemented from field programmable gate arrays (FPGAs), which are semiconductor devices that can be configured (and generally reconfigured) by the customer or designer after manufacturing and assembly (e.g., programmed via programming software). FPGAs are conventionally programmed using a logic circuit diagram or a source code in a hardware description language (HDL) to specify how the chip will function (e.g., filter design, sampling rates).
Some recent AWGs provide Field Programmable Gate Array (FPGA) based Real-Time Signal Processing (RTSP) for Digital Up Conversion (DUC) and interpolation by integer factors. One of the many advantages of this approach is the dramatic savings in waveform memory it allows. This saving comes because as the interpolation, or sample rate increases, and carrier modulation is performed in real time, so that it is only necessary to store the minimum number of samples required to reconstruct the baseband I/Q representation of the signal. Some such AWGs fix the clock sample rate of the DAC and allow the waveform to be stored in memory at an integer submultiple of the DAC sample rate. Interpolation by integer factors increases the sample rate of the waveform to the DAC sample rate in real time. This achieves some waveform memory compression and allows the use of a single reconstruction filter to eliminate DAC images. However, integer factor interpolation is inflexible since the choice of sample rates is quite restricted.
Other known AWGs provide two sample clocks. One sample clock provides a spectrally pure integer submultiple of the maximum clock rate for high performance, and the other sample clock offers the flexibility of high resolution frequency selection. Besides an extra (i.e. a second) sample clock that adds to the hardware complexity and cost, the wideband Spurious Free Dynamic Range (SFDR) of current integrated direct digital synthesis (DDS) chips is generally limited to the 40 to 60 dB range for typical sample rates approaching 100 MHz or more. These spurious components cause undesirable distortion in the output spectrum of the AWG which compromises spectral purity.